`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: tb_ALU
// Module Name: tb_ALU
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: Computes the sum, multiplication, and comparison of the values in the reg set,
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////

module tb_ALU;

	// Inputs
	reg CMP;
	reg SUM;
	reg MUL;
	reg [3:0] rega;
	reg [3:0] regb;
	reg clk;
	// Outputs
	wire [7:0] result;

	// Instantiate the Unit Under Test (UUT)
	ALU uut (
		.CMP(CMP), 
		.SUM(SUM), 
		.MUL(MUL), 
		.rega(rega), 
		.regb(regb), 
		.result(result)
	);

	initial begin
		// Initialize Inputs
		CMP = 0;
		SUM = 0;
		MUL = 0;
		rega = 0;
		regb = 0;
		clk = 0;

		forever #5 clk <= ~clk;
		end
		initial begin
			@(posedge clk) CMP=0;	SUM=0;	MUL=0;	rega=4'b0000;	regb=4'b0000;
			@(posedge clk) CMP=0;	SUM=0;	MUL=0;	rega=4'b0000;	regb=4'b0000;
			@(posedge clk) CMP=1;	SUM=0;	MUL=0;	rega=4'b0000;	regb=4'b0000;
			@(posedge clk) CMP=0;	SUM=1;	MUL=0;	rega=4'b0001;	regb=4'b0001;
			@(posedge clk) CMP=0;	SUM=0;	MUL=1;	rega=4'b0010;	regb=4'b0100;
			@(posedge clk) CMP=1;	SUM=0;	MUL=0;	rega=4'b0000;	regb=4'b0001;
			@(posedge clk) CMP=0;	SUM=1;	MUL=0;	rega=4'b1111;	regb=4'b0011;
			@(posedge clk) CMP=1;	SUM=1;	MUL=1;	rega=4'b0001;	regb=4'b0010;
			@(posedge clk) CMP=0;	SUM=0;	MUL=0;	rega=4'b0000;	regb=4'b0000;
		end
      
endmodule

